A method and amplifier arrangement to control the quiescent current are already known in the art, e.g. from the article “A 3.3 V Low-distortion ISDN Line Driver with a Novel Quiescent Current Control Circuit”, written by H. Casier, P. Wouters, B. Graindourze and D. Sallaerts, IEEE Journal of Solid-State Circuits, Vol. 33, Nr 7, July 1998, pp. 1130-1133. Therein, on page 1132, an amplifier arrangement including a quiescent current control circuit is shown and described. Basically, the currents flowing in each of the two output branches of the output stage of the operational amplifier are sensed and compared in a comparator, which consists of a simple inverter and a phase detector. Comparison with a reference current Iref is performed. The output of the comparator is fed back to the input stage of the amplifier arrangement via a charge pump circuit which charges or discharges a hold capacitor, dependent on this comparator output signal: if both sensed output currents are higher than the target reference or quiescent current, the capacitor is discharged; if both sensed output currents are lower than the target quiescent current, the capacitor is charged. The charge on the capacitor is further transformed via a buffer and an attenuator into a voltage difference between the positive input terminals of both error amplifiers preceding the output stage. This voltage difference, corresponding to the quiescent offset voltage, can be considered as a change in the input offset voltage of both amplifiers.
A drawback of this prior art method is however that the quiescent current level is set statically, thus without any frequency dependency. Therefore the quiescent current has to be dimensioned for the worst-case signal, i.e. the input signal which is the highest in frequency. This however results in a waste of power, as the quiescent current is thereby over-dimensioned for the lower frequency signals.